ECE 385
Fall 2017 Part of Term 1
Aug 28-Dec 13
Credit: 3 hours.
Design, build, and test digital systems using transistor-transistor logic (TTL), SystemVerilog, and field-programmable gate arrays (FPGAs). Topics include combinational and sequential logic, storage elements, input/output and display, timing analysis, design tradeoffs, synchronous and asynchronous design methods, datapath and controller, microprocessor design, software/hardware co-design, and system-on-a-chip.
Prerequisite: ECE 110 and ECE 220.
Students must register for one lab and one lecture section.
| CRN | Type | Section | Time | Day | Location | Instructor | Section Details | |
|---|---|---|---|---|---|---|---|---|
|
36843
|
Laboratory
|
AB1
|
8:00AM
-10:50AM
|
F
|
Electrical & Computer Eng Bldg
|
|
||
|
36856
|
Laboratory
|
AB2
|
3:00PM
-5:50PM
|
F
|
Electrical & Computer Eng Bldg
|
|
||
|
36821
|
Laboratory
|
AB3
|
2:00PM
-4:50PM
|
R
|
Electrical & Computer Eng Bldg
|
|
||
|
36823
|
Laboratory
|
AB4
|
8:00AM
-10:50AM
|
R
|
Electrical & Computer Eng Bldg
|
|
||
|
36826
|
Laboratory
|
AB5
|
11:00AM
-1:50PM
|
R
|
Electrical & Computer Eng Bldg
|
|
||
|
36835
|
Laboratory
|
AB6
|
12:00PM
-2:50PM
|
W
|
Electrical & Computer Eng Bldg
|
|
||
|
36829
|
Laboratory
|
AB7
|
11:00AM
-1:50PM
|
F
|
Electrical & Computer Eng Bldg
|
|
||
|
36838
|
Laboratory
|
AB8
|
9:00AM
-11:50AM
|
W
|
Electrical & Computer Eng Bldg
|
|
||
|
36773
|
Laboratory
|
ABC
|
2:00PM
-4:50PM
|
T
|
Electrical & Computer Eng Bldg
|
|
||
|
36803
|
Laboratory
|
ABD
|
8:00AM
-10:50AM
|
T
|
Electrical & Computer Eng Bldg
|
|
||
|
36805
|
Laboratory
|
ABE
|
11:00AM
-1:50PM
|
T
|
Electrical & Computer Eng Bldg
|
|
||
|
36720
|
Lecture
|
AL1
|
4:00PM
-4:50PM
|
MW
|
Electrical & Computer Eng Bldg
|
Cheng, Z
|
|