ECE 462

Fall 2016 Part of Term 1

Part of Term 1
Aug 22-Dec 7

Logic Synthesis

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Credit: 3 hours.

Unate function theory, unate recursive paradigm, synthesis of two-level logic, synthesis of incompletely specified combinational logic, multi-level logic synthesis, binary decision diagrams, finite state machine synthesis, automatic test pattern generation and design for test, equivalence checking and reachability analysis of finite machines, and technology mapping.

3 undergraduate hours. 3 graduate hours. Prerequisite: ECE 220 or CS 233.

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ECE 462 class schedule data for fall 2016
	CRN	Type	Section	Time	Day	Location	Instructor	Section Details
	56118	Discussion/ Recitation	D	11:00AM -12:20PM	TR	Electrical & Computer Eng Bldg	Patel, J	Part of Term: 1 Date Range: 08/22/16-12/07/16 Credit: 3 hours