ECE 385
Spring 2020 All Classes
Credit: 3 hours.
Design, build, and test digital systems using transistor-transistor logic (TTL), SystemVerilog, and field-programmable gate arrays (FPGAs). Topics include combinational and sequential logic, storage elements, input/output and display, timing analysis, design tradeoffs, synchronous and asynchronous design methods, datapath and controller, microprocessor design, software/hardware co-design, and system-on-a-chip.
Prerequisite: ECE 110 and ECE 220.
Students must register for one lab and one lecture section.
| CRN | Type | Section | Time | Day | Location | Instructor | Section Details | |
|---|---|---|---|---|---|---|---|---|
|
32768
|
Laboratory
|
ABB
|
11:00AM
-1:50PM
|
F
|
Electrical & Computer Eng Bldg
|
Liang, Y
|
|
|
|
32769
|
Laboratory
|
ABC
|
11:30AM
-2:20PM
|
T
|
Electrical & Computer Eng Bldg
|
Shiue, G
Zhang, D |
|
|
|
32770
|
Laboratory
|
ABD
|
6:00PM
-8:50PM
|
T
|
Electrical & Computer Eng Bldg
|
Cebry, N
Pan, W |
|
|
|
32771
|
Laboratory
|
ABE
|
3:00PM
-5:50PM
|
T
|
Electrical & Computer Eng Bldg
|
Liu, J
Zhang, D |
|
|
|
32773
|
Laboratory
|
ABG
|
12:00PM
-2:50PM
|
W
|
Electrical & Computer Eng Bldg
|
Cebry, N
Zhou, Y |
|
|
|
32774
|
Laboratory
|
ABH
|
8:00AM
-10:50AM
|
F
|
Electrical & Computer Eng Bldg
|
Pan, W
|
|
|
|
32775
|
Laboratory
|
ABI
|
8:00AM
-10:50AM
|
T
|
Electrical & Computer Eng Bldg
|
Liu, J
|
|
|
|
32776
|
Laboratory
|
ABJ
|
2:00PM
-4:50PM
|
F
|
Electrical & Computer Eng Bldg
|
Wu, Y
Yu, L |
|
|
|
32778
|
Laboratory
|
ABL
|
8:00AM
-10:50AM
|
R
|
Electrical & Computer Eng Bldg
|
Yun, K
|
|
|
|
32779
|
Laboratory
|
ABM
|
11:30AM
-2:20PM
|
R
|
Electrical & Computer Eng Bldg
|
Liang, Y
Yun, K |
|
|
|
32781
|
Laboratory
|
ABO
|
3:00PM
-5:50PM
|
R
|
Electrical & Computer Eng Bldg
|
Shiue, G
|
|
|
|
32782
|
Lecture
|
AL1
|
4:00PM
-4:50PM
|
MW
|
Electrical & Computer Eng Bldg
|
Cheng, Z
|
|
|
|
32777
|
Lecture
|
ALZ
|
4:00PM
-4:50PM
|
MW
|
Electrical & Computer Eng Bldg
|
Cheng, Z
|
|